Integrated circuit dimensions continue to be reduced due to various factors, such as cost per unit function considerations, faster required switching speeds, and desire for lower power consumption. Optical lithographic limitations are currently one of the major factors limiting size reduction in integrated circuit fabrication. Current projections forecast the lower limit of optical photolithography techniques currently under consideration to be less than 0.5 microns. However these techniques require further development to allow submicron fabrication using optical photolithography to be effectively transferred from the design laboratory to production fabrication facilities.
The optical lithographic processes of the prior art have several limitations which have heretofore blocked significant reduction in feature sizing in integrated circuit production. Examples of these limitations are described following. Optical lithographic apparatuses have physically limited depths of field, making it difficult or impossible to expose a thick photosensitive material through its thickness or to expose a layer of photosensitive material accurately which is not topographically planar at its surface. Depth of field is reduced as equipment is configured for smaller and smaller feature size. Wet etching and treating processes usually cause swelling of the remaining photosensitive material and other materials. Such swelling becomes more significant as feature size becomes smaller and prevents achievement of acceptable line to space ratios in some cases. Reflectivity of layer interfaces due to differing refractive indices of the materials causes diffusion and back scattering of the exposing radiation.
Efforts to overcome the limitations of standard optical lithographic equipment and techniques have been numerous and at least somewhat successful and continue to be a major thrust of semiconductor processing research. Multiple layer masks resulting in a thin planar photosensitive surface layer to be optically exposed, various exposure radiation sources and distances, closer tolerance optical equipment, and, in general, optimization of all process parameters relative to each other in the optical lithographic process have all contributed to reducing the minimum feature size possible in integrated circuit production. All of these approaches continue to be studied. However, there continues to be a need for further size reduction and, concurrently, avoidance of the more complicated and costly process steps necessary in some of the techniques to reduce sizing.
A promising development in the continued research to reduce obtainable sizing in optical lithography is advanced by B. Roland and A. Vrancken in "Method for the Preparation of Negative Patterns in a Layer of Photosensitive Resist", European Patent Number 184,567 A1, filed Oct. 24, 1985, "Method for Producing Positive Patterns in a Photoresist Layer," European Patent Number 248,779 A1, published Sept. 12, 1987, and further discussed in "DESIRE: A Novel Dry Developed Resist System", F. Coppmans et al., Advances in Resist Technology and Processing III, SPIE Proceedings, Vol. 631 (1986). This development followed closely the more general concepts advanced by G. N. Taylor, et al., in "Gas-Phase-Functionalized Plasma-Developed Resists: Initial Concepts and Results for Electron-Beam Exposure", Journal of the Electrochemical Society, Vol. 131, No. 7 (July 1984). These references, to the extent allowable, are incorporated herein by reference. This technique, as has been developed, is described generally in the following paragraphs.
The process generally consists of coating a substrate with a layer of photosensitive resin containing a polymer, preferably a phenolic polymer mixed with or bound to a photosensitive compound such as diazoquinone, exposure of this layer to visible or ultraviolet light through a mask, treating of the exposed layer to a silicon containing compound such as hexamethyldisilane in gas state although a liquid state treatment is possible, and then dry etching of the layer with a plasma such as by an oxygen plasma etch. The silylation is described as being accomplished in a chamber at reduced pressure generally with the substrate and resist layer being heated to a relatively high temperature. The extent of silylation is generally controlled by the length of time exposed to the silylating agent. As pointed out by Roland and Coppmans in the references above, the treatment of the photosensitive layer after exposure results in silylation of the exposed (unmasked) areas of the photosensitive layer with little or no silylation of the unexposed (masked) areas for negative pattern photosensitive resists or, alternately, heavy silylation of the unexposed areas with little or no silylation of the exposed areas for a positive pattern photosensitive resist. Further, discussion will exemplify the use of the negative pattern photosensitive resist, however, it will be understood that the inventive process and apparatus apply equally to both. Silylation, as defined in Silylation of Organic Compounds, by A. Pierce, Pierce Chemical Company, pages 1-3, and further explored in "Mechanism and Kinetics of Silylation of Resist Layers from the Gas Phase", R. Visser, et al., SPIE, Vol. 87, is the introduction of the silyl group (generally --Si(CH3)3) into a molecule, generally by replacement of a hydrogen. In the case of silylation of a resist layer, the silylating agent diffuses into and reacts with the exposed resin of the resist layer according to the generalized formula: ##STR1##
The kinetics of the reaction, particularly the rate of diffusion, cause the silylation to be highly selective to the exposed areas of the photoresist and to be restricted to only the near surface of the resist layer, e.g., the top 1000 to 10,000 Angstroms. Deeper exposures of the photoresist layer may be limited by techniques such as dying of the photoresist material. An anisotropic plasma etch, particularly an oxygen plasma etch, causes the incorporated silicon to form silicon dioxide which acts as an in-situ mask for the etch, oxygen plasma etching being highly selective to the silicon dioxide compared to the remainder of the resist.
This process presents several advantages for optical lithography. Since the silylation is restricted to only the topmost portion of the resist layer, exposure depth may be restricted to only that depth or, in any case, deeper exposure which may not be accurately focused becomes less important. This greatly reduces depth of field problems and the problems associated with diffusion of the exposure radiation. A dry etching process may be used to develop the resist layer because of the high selectivity of a plasma etch to the silylated regions. Therefore the problems caused by wet etching techniques are eliminated. Because the silylation is highly selective to the exposed versus unexposed portions of the resist layer, acceptably precise mask layers may be produced from the resist layer.
There are, however, problems associated with the above described process. Exposure of the resist layer to the silylating agent is described in the references as being accomplished at high temperatures and for relatively long time periods, especially if the temperature is not high. Control of the extent of silylation has been difficult. Silylation has been described in the literature as being accomplished at low pressures, requiring vacuum or low pressure processing receptacles.